by Cetinkaya, H., Zeki, A., Girgin, A., Karabeyoglu, E.D. and Karalar, T.C.
Reference:
Cetinkaya, H., Zeki, A., Girgin, A., Karabeyoglu, E.D. and Karalar, T.C., "A 1.6 GHz Non-overlap Clock Generation with Differential Clock Driver and Clock Level Shifters for GS/s Sampling Rate Pipeline ADCs", 2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018, pp. 277-280, 2018.
Bibtex Entry:
@CONFERENCE{Cetinkaya2019277,
author={Cetinkaya, H. and Zeki, A. and Girgin, A. and Karabeyoglu, E.D. and Karalar, T.C.},
title={A 1.6 GHz Non-overlap Clock Generation with Differential Clock Driver and Clock Level Shifters for GS/s Sampling Rate Pipeline ADCs},
journal={2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018},
year={2018},
pages={277-280},
doi={10.1109/ICECS.2018.8618005},
art_number={8618005},
url={https://www.scopus.com/inward/record.uri?eid=2-s2.0-85062259603&doi=10.1109%2fICECS.2018.8618005&partnerID=40&md5=198987edef699547bf47b73843e090e2},
language={English},
document_type={Conference Paper},
source={Scopus},
}