by Parvin, S. and Altun, M.
Reference:
Parvin, S. and Altun, M., "Perfect Concurrent Fault Detection in CMOS Logic Circuits Using Parity Preservative Reversible Gates", In IEEE Access, vol. 7, pp. 163939-163947, 2019.
Bibtex Entry:
@ARTICLE{Parvin2019163939, author={Parvin, S. and Altun, M.}, title={Perfect Concurrent Fault Detection in CMOS Logic Circuits Using Parity Preservative Reversible Gates}, journal={IEEE Access}, year={2019}, volume={7}, pages={163939-163947}, doi={10.1109/ACCESS.2019.2951279}, art_number={8890724}, url={https://www.scopus.com/inward/record.uri?eid=2-s2.0-85077522166&doi=10.1109%2fACCESS.2019.2951279&partnerID=40&md5=ca8bf9741bf1ba85f52df102dd304e91}, language={English}, document_type={Article}, source={Scopus}, }