by Parvin, S. and Altun, M.
Reference:
Parvin, S. and Altun, M., "Implementation of CMOS Logic Circuits with Perfect Fault Detection Using Preservative Reversible Gates", 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design, IOLTS 2019, pp. 64-67, 2019.
Bibtex Entry:
@CONFERENCE{Parvin201964,
author={Parvin, S. and Altun, M.},
title={Implementation of CMOS Logic Circuits with Perfect Fault Detection Using Preservative Reversible Gates},
journal={2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design, IOLTS 2019},
year={2019},
pages={64-67},
doi={10.1109/IOLTS.2019.8854440},
art_number={8854440},
url={https://www.scopus.com/inward/record.uri?eid=2-s2.0-85073717951&doi=10.1109%2fIOLTS.2019.8854440&partnerID=40&md5=899091ff6422de6b03fb3809de58f81d},
language={English},
document_type={Conference Paper},
source={Scopus},
}